Note: Be sure to complete Reading 6 and read this entire project description before hacking away.

Project 6 (ecs01)

Jan 25, 2010

Objective

Implement all the logic gates presented in Chapter 1. The only building blocks that you can use are primitive Nand gates and the composite gates that you will gradually build on top of them.

Requirements

Read ECS chapter 1.

Review ECS Appendix A 5.1 and 5.2.

Referring to the two-variable boolean functions table on TECS page 10, this boolean proofs pdf and the algebraic examples in CODE may be helpful.

Within your src directory, create a subdir named project01. Extract the contents of project 01.zip into it.

Your file structure should now look like:

Add, commit and push the new files.

While working on this project, be sure to commit often. I usually commit one time per each .hdl once I know it's passing my tests. Once you're done with the entire project, push.

The only tool that you need for this project is the hardware simulator supplied with the book. All the chips should be implemented in the HDL language specified in Appendix A. For every one of the chips mentioned in Chapter 1, we provide a skeletal .hdl program (text file) with a missing implementation part. In addition, for each chip we provide a .tst script file that tells the hardware simulator how to test it, along with the correct output file that this script should generate, called .cmp or "compare file". Your job is to complete the missing implementation parts of all the supplied .hdl programs.

When loaded into the Hardware Simulator, your chip design (modified .hdl program), tested on the supplied .tst file, should produce the outputs listed in the supplied .cmp file. If that is not the case, the simulator will let you know.

Example workflow

Let's say you want to start working on the Not chip.

1. Start the Hardware Emulator and load Not.tst
2. Run the script. Note that the chip will load and the test will fail.
3. Get the test to pass:
   1. Open Not.hdl in the editor of your choice and implement the chip.
   2. Save your changes.
   3. Re-run the test script (click 'reset' then 'run'). You should see your modified .hdl file in the lower left panel.
4. Once the chip is working (passes the test), commit your changes and move on to the next chip.

TIPS

The Nand gate is considered primitive and thus there is no need to build it: whenever you use Nand in one of your HDL programs, the simulator automatically invokes the built-in builtInChips/Nand.hdl implementation. I recommend implementing the gates in this project in the order in which they appear in the chapter. (However, since the simulator features built-in versions of all these chips, you can always use the chips without defining them first: the simulator will automatically invoke their built-in versions).

For example, consider the skeletal Mux.hdl program supplied in this project. Suppose that for one reason or another you did not complete the implementation of Mux, but you still want to use Mux chips as internal parts in other chip designs. This is not a problem, thanks to the following convention. If our simulator fails to find a Mux.hdl file in the current directory, it automatically invokes a built-in Mux implementation, pre-supplied with the simulator’s software. This built-in Mux implementation -- a Java class stored in the simulator's builtIn directory -- has the same interface and functionality as those of the Mux chip described in the book. Thus, if you want the simulator to ignore one or more of your chip implementations, simply move the corresponding .hdl files out from the current directory.

Grading Criteria (300 pts)

I must be able to pull your repo at 5PM on Friday, January 29 and I should see your completed chip implementations in your project01 directory.

This is due by 5PM on Friday, January 29.