Learn about the hardware simulator environment and play with some built-in chips. Get acquainted with the concepts of chip testing and hardware simulation.
Read ECS through page 6. [pdf here]
Read parts I - III of the hardware simulator tutorial.
Within your src directory, create a subdir named project00. Extract the contents of project00.zip into it.
Your file structure should now look like:
Add, commit and push the new files.
Important: tell git to ignore .out and .output files
The test scripts often generate an output file from each chip you use, and then compares that output file to the provided .cmp file. We don't want to track these in the repository, so tell git to ignore them. Create the file cs498/src/.gitignore. It should contain the following lines:
Now add and commit the file.
Invoke the hardware simulator...
...and load one of the test scripts. Windows users: Do not execute the above script, just double-click on HardwareSimulator.bat.
Look at the script, displayed on the right panel of the Hardware Simulator (HS). Note that the first thing it does is load the chip.
Run the script. What happened? Note that the HW has loaded the chip, and you see the inputs and outputs. The script also generated a file called And.out, compared it to And.cmp, and the status bar at the bottom tells you that the comparison matched ("Comparison ended successfully").
Note that since the chip is now loaded, you can experiment with it directly, by changing the value of the inputs (eg, from 0 to 1 or vice versa), clicking the Eval button (it looks like a calculator), and seeing the resulting output.
Quickly load some of the other test scripts in project00 and play with the chips.
| Chip name | Function | Test scripts | Compare files |
|
And Mux8Way16 Register RAM8 |
And gate 16-bit 8-way multiplexor 16-bit register 8-register RAM |
Note that the And and Mux8Way16 chips are combinational, and the Register and RAM8 chips are sequential (clock-dependent). Therefore the latter two chips will make sense only after you read Chapter 3. (The point is, if you are playing with a clocked chip rather than a combinational chip, you have to use "TickTock" button instead of "Eval").
You will notice that some chips, e.g. RAM8, have a GUI. This GUI enables testing these chips visually.
Inside your tecs-software-suite-2.5/BuiltInChips directory are numerous "built-in" chips. What exactly is a built-in chip?
The activity described in this project is sometimes called "behavioral simulation" -- experimenting with the chip's functionality. For this purpose, there's no need to create a gate logic implementation of the chip. Instead, one can implement the chip logic using any other means, e.g. Java. And that's precisely what our built-in chips are -- Java classes that the hardware simulator is programmed to use each time it does not find an .hdl file in the current directory.
Later, you will load the chip's test script (.tst file), and run it. This will show you exactly what type of behavior is expected from the chip you are building. Needless to say, this knowledge is nice to have before you actually set out to build the chip in HDL.
Every chip that you will be asked to build in this course is accompanied by .tst and .cmp files. Therefore, you never have to guess what the chip is supposed to do -- you will receive an executable definition of this contract. In addition, for each chip you will receive a basic .hdl file that you are supposed to extend into a working HDL chip definition.
Tip: almost every chip that you will be asked to build has a pre-defined, built-in version. Therefore, if you want to experiment with the a chip before you set out to build it, simply load the respective .tst script into the hardware simulator and start the simulation. Since a typical .tst file begins with a command that tells the simulator to load the chip, the simulator will look for the .hdl file in the current directory, will not find it, and then open the built-in version of the chip instead. At this point you can experiment with the chip's functionality, exactly like you did in this project.
I must be able to pull your repo at 5PM on Friday, January 22 and I should see your project00 files.